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Bump OpenOCD Config Generator for Multicore Configs #452

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Mar 30, 2020
Merged

Bump OpenOCD Config Generator for Multicore Configs #452

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329ce22
Bump openocdcfg generator for multicore
nategraff-sifive Mar 27, 2020
c07ac84
Regen BSPs
nategraff-sifive Mar 27, 2020
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13 changes: 5 additions & 8 deletions bsp/freedom-e310-arty/openocd.cfg
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Original file line number Diff line number Diff line change
Expand Up @@ -43,22 +43,19 @@ switch ${debug_config} {
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen $chain_length

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
set _TARGETNAME_0 $_CHIPNAME.cpu

target create $_TARGETNAME_0 riscv -chain-position $_TARGETNAME_0

$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1
$_TARGETNAME_0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1

if { $chain_length == 6 } {
riscv use_bscan_tunnel 5
}

flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10014000
flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME_0 0x10014000

init
# If required, the authdata_write command must be added immediately after the 'init' command
# Use:
# riscv authdata_write ????????

if { [info exists authkey] } {
riscv authdata_write $authkey
}
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13 changes: 5 additions & 8 deletions bsp/freedom-e310-arty/openocd.cjtag.cfg
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Original file line number Diff line number Diff line change
Expand Up @@ -43,22 +43,19 @@ switch ${debug_config} {
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen $chain_length

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
set _TARGETNAME_0 $_CHIPNAME.cpu

target create $_TARGETNAME_0 riscv -chain-position $_TARGETNAME_0

$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1
$_TARGETNAME_0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1

if { $chain_length == 6 } {
riscv use_bscan_tunnel 5
}

flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10014000
flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME_0 0x10014000

init
# If required, the authdata_write command must be added immediately after the 'init' command
# Use:
# riscv authdata_write ????????

if { [info exists authkey] } {
riscv authdata_write $authkey
}
Expand Down
22 changes: 14 additions & 8 deletions bsp/sifive-hifive-unleashed/openocd.cfg
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Original file line number Diff line number Diff line change
Expand Up @@ -14,22 +14,28 @@ ftdi_layout_signal LED -data 0x0020
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen $chain_length

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
set _TARGETNAME_0 $_CHIPNAME.cpu0
set _TARGETNAME_1 $_CHIPNAME.cpu1
set _TARGETNAME_2 $_CHIPNAME.cpu2
set _TARGETNAME_3 $_CHIPNAME.cpu3
set _TARGETNAME_4 $_CHIPNAME.cpu4

target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -rtos hwthread
target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu -coreid 2
target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu -coreid 3
target create $_TARGETNAME_4 riscv -chain-position $_CHIPNAME.cpu -coreid 4
target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3 $_TARGETNAME_4

$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1
$_TARGETNAME_0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1

if { $chain_length == 6 } {
riscv use_bscan_tunnel 5
}

flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000
flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME_0 0x10040000

init
# If required, the authdata_write command must be added immediately after the 'init' command
# Use:
# riscv authdata_write ????????

if { [info exists authkey] } {
riscv authdata_write $authkey
}
Expand Down
13 changes: 5 additions & 8 deletions bsp/sifive-hifive1/openocd.cfg
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Original file line number Diff line number Diff line change
Expand Up @@ -14,22 +14,19 @@ ftdi_layout_signal LED -data 0x0020
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen $chain_length

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
set _TARGETNAME_0 $_CHIPNAME.cpu

target create $_TARGETNAME_0 riscv -chain-position $_TARGETNAME_0

$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1
$_TARGETNAME_0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1

if { $chain_length == 6 } {
riscv use_bscan_tunnel 5
}

flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10014000
flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME_0 0x10014000

init
# If required, the authdata_write command must be added immediately after the 'init' command
# Use:
# riscv authdata_write ????????

if { [info exists authkey] } {
riscv authdata_write $authkey
}
Expand Down
2 changes: 1 addition & 1 deletion scripts/openocdcfg-generator
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Submodule openocdcfg-generator updated 3 files
+4 −4 build.wake
+3 −0 generate_openocdcfg.py
+21 −8 templates/openocd.cfg
2 changes: 1 addition & 1 deletion wit-manifest.json
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@
"source": "[email protected]:sifive/cmsis-svd-generator.git"
},
{
"commit": "f418e6c39416a8003bf9388d718fea5498e77773",
"commit": "e91034b8b8e7994b2c23f9e7e7cfff36bf031a91",
"name": "openocdcfg-generator",
"source": "[email protected]:sifive/openocdcfg-generator.git"
},
Expand Down