Merge pull request #551 from sifive/kiwi2koala

Merging Kiwi features L2PM and L2PF
sifive · Sep 29, 2020 · 2d4fd8d · 2d4fd8d
2 parents 1ef7a30 + 012c78b
commit 2d4fd8d
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Showing 44 changed files with 99 additions and 240 deletions.
diff --git a/.gitmodules b/.gitmodules
@@ -154,3 +154,9 @@
 [submodule "scl-metal"]
 	path = scl-metal
 	url = https://github.com/sifive/scl-metal.git
+[submodule "software/example-l2pm"]
+	path = software/example-l2pm
+	url = https://github.com/sifive/example-l2pm.git
+[submodule "software/example-l2pf"]
+	path = software/example-l2pf
+	url = https://github.com/sifive/example-l2pf.git
diff --git a/FreeRTOS-metal b/FreeRTOS-metal
diff --git a/README.md b/README.md
@@ -149,6 +149,10 @@ operating systems to RISC-V.
     - A memory test that measure the latency at different cache layers and memory blocks
   - example-hpm
     - Demonstrates usage of the RISC-V hardware performance counter APIs.
+  - example-l2pm
+    - Demonstrates usage of Sifive L2 performance monitor counter APIs to capture L2 cache event logs.
+  - example-l2pf
+    - Example for usage and measuring effectiveness of SiFive L2 Prefetcher.
   - example-freertos-minimal
     - A simple FreeRTOS skeleton to build your FreeRTOS application.
   - example-freertos-blinky

diff --git a/bsp/freedom-e310-arty/metal-inline.h b/bsp/freedom-e310-arty/metal-inline.h
@@ -47,9 +47,6 @@ extern __inline__ int __metal_driver_sifive_plic0_context_ids(int hartid);
 /* --------------------- sifive_buserror0 ------------ */
 
 
-/* --------------------- sifive_ccache0 ------------ */
-
-
 /* --------------------- sifive_clic0 ------------ */
 
 
@@ -142,9 +139,6 @@ extern __inline__ unsigned long __metal_driver_sifive_uart0_pinmux_source_select
 /* --------------------- fe310_g000_prci ------------ */
 
 
-/* --------------------- sifive_fu540_c000_l2 ------------ */
-
-
 /* From clock@0 */
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,

diff --git a/bsp/freedom-e310-arty/metal.h b/bsp/freedom-e310-arty/metal.h
@@ -331,9 +331,6 @@ static __inline__ int __metal_driver_sifive_plic0_context_ids(int hartid)
 /* --------------------- sifive_buserror0 ------------ */
 
 
-/* --------------------- sifive_ccache0 ------------ */
-
-
 /* --------------------- sifive_clic0 ------------ */
 
 
@@ -825,9 +822,6 @@ static __inline__ unsigned long __metal_driver_sifive_uart0_pinmux_source_select
 /* --------------------- sifive_fe310_g000_prci ------------ */
 
 
-/* --------------------- sifive_fu540_c000_l2 ------------ */
-
-
 #define __METAL_DT_MAX_MEMORIES 3
 
 __asm__ (".weak __metal_memory_table");

diff --git a/bsp/freedom-e310-arty/metal.scratchpad.lds b/bsp/freedom-e310-arty/metal.scratchpad.lds
@@ -72,16 +72,8 @@ SECTIONS
      * certain core features */
     PROVIDE(__metal_chicken_bit = 1);
 
-    /* The memory_ecc_scrub bit is used by _entry code to enable/disable
-     * memories scrubbing to zero  */
     PROVIDE(__metal_eccscrub_bit = 0);
 
-    /* The RAM memories map for ECC scrubbing */
-    PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
-    PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x4000 );
-    PROVIDE( metal_itim_0_memory_start = 0x8000000 );
-    PROVIDE( metal_itim_0_memory_end = 0x8000000 + 0x4000 );
-
     /* ROM SECTION
      *
      * The following sections contain data which lives in read-only memory, if

diff --git a/bsp/qemu-sifive-e31/metal-inline.h b/bsp/qemu-sifive-e31/metal-inline.h
@@ -47,9 +47,6 @@ extern __inline__ int __metal_driver_sifive_plic0_context_ids(int hartid);
 /* --------------------- sifive_buserror0 ------------ */
 
 
-/* --------------------- sifive_ccache0 ------------ */
-
-
 /* --------------------- sifive_clic0 ------------ */
 
 
@@ -178,9 +175,6 @@ extern __inline__ long __metal_driver_sifive_fe310_g000_prci_size( );
 extern __inline__ const struct __metal_driver_vtable_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_prci_vtable( );
 
 
-/* --------------------- sifive_fu540_c000_l2 ------------ */
-
-
 /* From clock@0 */
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,

diff --git a/bsp/qemu-sifive-e31/metal.h b/bsp/qemu-sifive-e31/metal.h
@@ -383,9 +383,6 @@ static __inline__ int __metal_driver_sifive_plic0_context_ids(int hartid)
 /* --------------------- sifive_buserror0 ------------ */
 
 
-/* --------------------- sifive_ccache0 ------------ */
-
-
 /* --------------------- sifive_clic0 ------------ */
 
 
@@ -1170,9 +1167,6 @@ static __inline__ const struct __metal_driver_vtable_sifive_fe310_g000_prci * __
 
 
 
-/* --------------------- sifive_fu540_c000_l2 ------------ */
-
-
 #define __METAL_DT_MAX_MEMORIES 2
 
 __asm__ (".weak __metal_memory_table");

diff --git a/bsp/qemu-sifive-e31/metal.scratchpad.lds b/bsp/qemu-sifive-e31/metal.scratchpad.lds
@@ -71,16 +71,8 @@ SECTIONS
      * certain core features */
     PROVIDE(__metal_chicken_bit = 1);
 
-    /* The memory_ecc_scrub bit is used by _entry code to enable/disable
-     * memories scrubbing to zero  */
     PROVIDE(__metal_eccscrub_bit = 0);
 
-    /* The RAM memories map for ECC scrubbing */
-    /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
-    /* User is recommended to enable the full size for manual RTL simulation run! */
-    PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
-    PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 );
-
     /* ROM SECTION
      *
      * The following sections contain data which lives in read-only memory, if

diff --git a/bsp/qemu-sifive-s51/metal-inline.h b/bsp/qemu-sifive-s51/metal-inline.h
@@ -47,9 +47,6 @@ extern __inline__ int __metal_driver_sifive_plic0_context_ids(int hartid);
 /* --------------------- sifive_buserror0 ------------ */
 
 
-/* --------------------- sifive_ccache0 ------------ */
-
-
 /* --------------------- sifive_clic0 ------------ */
 
 
@@ -178,9 +175,6 @@ extern __inline__ long __metal_driver_sifive_fe310_g000_prci_size( );
 extern __inline__ const struct __metal_driver_vtable_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_prci_vtable( );
 
 
-/* --------------------- sifive_fu540_c000_l2 ------------ */
-
-
 /* From clock@0 */
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,

diff --git a/bsp/qemu-sifive-s51/metal.h b/bsp/qemu-sifive-s51/metal.h
@@ -383,9 +383,6 @@ static __inline__ int __metal_driver_sifive_plic0_context_ids(int hartid)
 /* --------------------- sifive_buserror0 ------------ */
 
 
-/* --------------------- sifive_ccache0 ------------ */
-
-
 /* --------------------- sifive_clic0 ------------ */
 
 
@@ -1170,9 +1167,6 @@ static __inline__ const struct __metal_driver_vtable_sifive_fe310_g000_prci * __
 
 
 
-/* --------------------- sifive_fu540_c000_l2 ------------ */
-
-
 #define __METAL_DT_MAX_MEMORIES 2
 
 __asm__ (".weak __metal_memory_table");

diff --git a/bsp/qemu-sifive-s51/metal.scratchpad.lds b/bsp/qemu-sifive-s51/metal.scratchpad.lds
@@ -71,16 +71,8 @@ SECTIONS
      * certain core features */
     PROVIDE(__metal_chicken_bit = 1);
 
-    /* The memory_ecc_scrub bit is used by _entry code to enable/disable
-     * memories scrubbing to zero  */
     PROVIDE(__metal_eccscrub_bit = 0);
 
-    /* The RAM memories map for ECC scrubbing */
-    /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
-    /* User is recommended to enable the full size for manual RTL simulation run! */
-    PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
-    PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 );
-
     /* ROM SECTION
      *
      * The following sections contain data which lives in read-only memory, if

diff --git a/bsp/qemu-sifive-u54/core.dts b/bsp/qemu-sifive-u54/core.dts
@@ -16,7 +16,7 @@
 			reg = <0x0>;
 			status = "okay";
 			compatible = "riscv";
-			riscv,isa = "rv64imafdcsu";
+			riscv,isa = "rv64imafdc";
 			mmu-type = "riscv,sv48";
 			clock-frequency = <0x3b9aca00>;
 			riscv,pmpregions = <8>;

diff --git a/bsp/qemu-sifive-u54/metal-inline.h b/bsp/qemu-sifive-u54/metal-inline.h
@@ -46,9 +46,6 @@ extern __inline__ int __metal_driver_sifive_plic0_context_ids(int hartid);
 /* --------------------- sifive_buserror0 ------------ */
 
 
-/* --------------------- sifive_ccache0 ------------ */
-
-
 /* --------------------- sifive_clic0 ------------ */
 
 
@@ -117,9 +114,6 @@ extern __inline__ unsigned long __metal_driver_sifive_uart0_pinmux_source_select
 /* --------------------- fe310_g000_prci ------------ */
 
 
-/* --------------------- sifive_fu540_c000_l2 ------------ */
-
-
 struct metal_memory __metal_dt_mem_memory_80000000 = {
     ._base_address = 2147483648UL,
     ._size = 2147483648UL,

diff --git a/bsp/qemu-sifive-u54/metal.h b/bsp/qemu-sifive-u54/metal.h
@@ -304,9 +304,6 @@ static __inline__ int __metal_driver_sifive_plic0_context_ids(int hartid)
 /* --------------------- sifive_buserror0 ------------ */
 
 
-/* --------------------- sifive_ccache0 ------------ */
-
-
 /* --------------------- sifive_clic0 ------------ */
 
 
@@ -474,9 +471,6 @@ static __inline__ unsigned long __metal_driver_sifive_uart0_pinmux_source_select
 /* --------------------- sifive_fe310_g000_prci ------------ */
 
 
-/* --------------------- sifive_fu540_c000_l2 ------------ */
-
-
 #define __METAL_DT_MAX_MEMORIES 1
 
 __asm__ (".weak __metal_memory_table");

diff --git a/bsp/qemu-sifive-u54/metal.scratchpad.lds b/bsp/qemu-sifive-u54/metal.scratchpad.lds
@@ -70,16 +70,8 @@ SECTIONS
      * certain core features */
     PROVIDE(__metal_chicken_bit = 1);
 
-    /* The memory_ecc_scrub bit is used by _entry code to enable/disable
-     * memories scrubbing to zero  */
     PROVIDE(__metal_eccscrub_bit = 0);
 
-    /* The RAM memories map for ECC scrubbing */
-    /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
-    /* User is recommended to enable the full size for manual RTL simulation run! */
-    PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
-
     /* ROM SECTION
      *
      * The following sections contain data which lives in read-only memory, if

diff --git a/bsp/qemu-sifive-u54/settings.mk b/bsp/qemu-sifive-u54/settings.mk
@@ -1,7 +1,7 @@
 # Copyright (C) 2020 SiFive Inc
 # SPDX-License-Identifier: Apache-2.0
 
-RISCV_ARCH = rv64imafdcsu
+RISCV_ARCH = rv64imafdc
 RISCV_ABI = lp64d
 RISCV_CMODEL = medany
 RISCV_SERIES = None

diff --git a/bsp/qemu-sifive-u54mc/core.dts b/bsp/qemu-sifive-u54mc/core.dts
@@ -16,7 +16,7 @@
 			reg = <0x0>;
 			status = "okay";
 			compatible = "riscv";
-			riscv,isa = "rv64imafdcsu";
+			riscv,isa = "rv64imafdc";
 			mmu-type = "riscv,sv48";
 			clock-frequency = <0x3b9aca00>;
 			riscv,pmpregions = <8>;

diff --git a/bsp/qemu-sifive-u54mc/metal-inline.h b/bsp/qemu-sifive-u54mc/metal-inline.h
@@ -47,9 +47,6 @@ extern __inline__ int __metal_driver_sifive_plic0_context_ids(int hartid);
 /* --------------------- sifive_buserror0 ------------ */
 
 
-/* --------------------- sifive_ccache0 ------------ */
-
-
 /* --------------------- sifive_clic0 ------------ */
 
 
@@ -120,9 +117,6 @@ extern __inline__ unsigned long __metal_driver_sifive_uart0_pinmux_source_select
 /* --------------------- fe310_g000_prci ------------ */
 
 
-/* --------------------- sifive_fu540_c000_l2 ------------ */
-
-
 /* From ethclk */
 struct __metal_driver_fixed_clock __metal_dt_ethclk = {
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,

diff --git a/bsp/qemu-sifive-u54mc/metal.h b/bsp/qemu-sifive-u54mc/metal.h
@@ -458,9 +458,6 @@ static __inline__ int __metal_driver_sifive_plic0_context_ids(int hartid)
 /* --------------------- sifive_buserror0 ------------ */
 
 
-/* --------------------- sifive_ccache0 ------------ */
-
-
 /* --------------------- sifive_clic0 ------------ */
 
 
@@ -628,9 +625,6 @@ static __inline__ unsigned long __metal_driver_sifive_uart0_pinmux_source_select
 /* --------------------- sifive_fe310_g000_prci ------------ */
 
 
-/* --------------------- sifive_fu540_c000_l2 ------------ */
-
-
 #define __METAL_DT_MAX_MEMORIES 1
 
 __asm__ (".weak __metal_memory_table");

diff --git a/bsp/qemu-sifive-u54mc/metal.scratchpad.lds b/bsp/qemu-sifive-u54mc/metal.scratchpad.lds
@@ -70,16 +70,8 @@ SECTIONS
      * certain core features */
     PROVIDE(__metal_chicken_bit = 1);
 
-    /* The memory_ecc_scrub bit is used by _entry code to enable/disable
-     * memories scrubbing to zero  */
     PROVIDE(__metal_eccscrub_bit = 0);
 
-    /* The RAM memories map for ECC scrubbing */
-    /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
-    /* User is recommended to enable the full size for manual RTL simulation run! */
-    PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
-
     /* ROM SECTION
      *
      * The following sections contain data which lives in read-only memory, if

diff --git a/bsp/qemu-sifive-u54mc/settings.mk b/bsp/qemu-sifive-u54mc/settings.mk
@@ -1,7 +1,7 @@
 # Copyright (C) 2020 SiFive Inc
 # SPDX-License-Identifier: Apache-2.0
 
-RISCV_ARCH = rv64imafdcsu
+RISCV_ARCH = rv64imafdc
 RISCV_ABI = lp64d
 RISCV_CMODEL = medany
 RISCV_SERIES = None

diff --git a/bsp/sifive-hifive-unleashed/metal-inline.h b/bsp/sifive-hifive-unleashed/metal-inline.h
@@ -50,9 +50,6 @@ extern __inline__ int __metal_driver_sifive_plic0_context_ids(int hartid);
 /* --------------------- sifive_buserror0 ------------ */
 
 
-/* --------------------- sifive_ccache0 ------------ */
-
-
 /* --------------------- sifive_clic0 ------------ */
 
 
@@ -153,10 +150,6 @@ extern __inline__ unsigned long __metal_driver_sifive_uart0_pinmux_source_select
 /* --------------------- fe310_g000_prci ------------ */
 
 
-/* --------------------- sifive_fu540_c000_l2 ------------ */
-extern __inline__ uintptr_t __metal_driver_sifive_fu540_c000_l2_control_base(struct metal_cache *cache);
-
-
 /* From refclk */
 struct __metal_driver_fixed_clock __metal_dt_refclk = {
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
@@ -397,11 +390,6 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000 = {
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
 };
 
-/* From cache_controller@2010000 */
-struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = {
-    .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache,
-};
-
 
 #endif /* METAL_INLINE_H*/
 #endif /* ! ASSEMBLY */