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Merge pull request #359 from sifive/bump-freedom-devicetree-tools
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Pull in latest changes from master and forward-port recent changes from v201908-branch
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nategraff-sifive authored Sep 9, 2019
2 parents 1755333 + 25ef66e commit 12f6e96
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Showing 53 changed files with 776 additions and 828 deletions.
14 changes: 14 additions & 0 deletions bsp/freedom-e310-arty/README.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
The [Freedom E310 Arty](https://github.com/sifive/freedom) is a completely open-source
implementation of RISC-V using the Rocket Chip Generator, designed for use with
the [Digilent Arty FPGA Evaluation Kit](https://www.xilinx.com/products/boards-and-kits/arty.html).

This target is ideal for getting familiarize with RISC-V ISA instructions set and
freedom-metal libraries. It supports:

- 1 hart with RV32IMAC core
- 4 hardware breakpoints
- 16 local interrupts signal that can be connected to off core complex devices
- Up to 26 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
- GPIO with 16 interrupt lines
- SPI memory with 1 interrupt line
- Serial port with 1 interrupt line
3 changes: 3 additions & 0 deletions bsp/freedom-e310-arty/metal-inline.h
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@ extern __inline__ int __metal_driver_sifive_plic0_num_interrupts(struct metal_in
extern __inline__ int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
extern __inline__ struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
extern __inline__ int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
extern __inline__ int __metal_driver_sifive_plic0_context_ids(int hartid);


/* --------------------- sifive_clic0 ------------ */
Expand Down Expand Up @@ -85,6 +86,8 @@ extern __inline__ unsigned long __metal_driver_sifive_spi0_pinmux_source_selecto
/* --------------------- sifive_test0 ------------ */


/* --------------------- sifive_trace ------------ */

/* --------------------- sifive_uart0 ------------ */
extern __inline__ unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
extern __inline__ unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
Expand Down
7 changes: 5 additions & 2 deletions bsp/freedom-e310-arty/metal-platform.h
Original file line number Diff line number Diff line change
Expand Up @@ -36,8 +36,11 @@
#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
#define METAL_RISCV_PLIC0_CLAIM 2097156UL
#define METAL_RISCV_PLIC0_ENABLE_PER_HART 128UL
#define METAL_RISCV_PLIC0_CONTEXT_BASE 2097152UL
#define METAL_RISCV_PLIC0_CONTEXT_PER_HART 4096UL
#define METAL_RISCV_PLIC0_CONTEXT_THRESHOLD 0UL
#define METAL_RISCV_PLIC0_CONTEXT_CLAIM 4UL

/* From gpio@10012000 */
#define METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS 268509184UL
Expand Down
64 changes: 27 additions & 37 deletions bsp/freedom-e310-arty/metal.default.lds
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ SECTIONS

__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x800;
PROVIDE(__metal_boot_hart = 0);
PROVIDE(__metal_chicken_bit = 0);

Expand Down Expand Up @@ -79,13 +79,21 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
PROVIDE_HIDDEN ( metal_constructors_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.metal.init_array.*)));
KEEP (*(.metal.init_array));
PROVIDE_HIDDEN ( metal_constructors_end = .);
} >flash AT>flash :flash

.fini_array : {
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
PROVIDE_HIDDEN ( metal_destructors_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.metal.fini_array.*)));
KEEP (*(.metal.fini_array));
PROVIDE_HIDDEN ( metal_destructors_end = .);
} >flash AT>flash :flash

.ctors : {
Expand All @@ -94,6 +102,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*(.metal.ctors metal.ctors.*));
} >flash AT>flash :flash

.dtors : {
Expand All @@ -102,39 +111,21 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
KEEP (*(.metal.dtors metal.dtors.*));
} >flash AT>flash :flash



.litimalign : {
. = ALIGN(8);
PROVIDE( metal_segment_itim_source_start = . );
} >flash AT>flash :flash

.ditimalign : {
. = ALIGN(8);
PROVIDE( metal_segment_itim_target_start = . );
} >itim AT>flash :itim_init

.itim_section : {
.itim : ALIGN(8) {
*(.itim .itim.*)
} >itim AT>flash :itim_init

PROVIDE( metal_segment_itim_target_end = . );

PROVIDE( metal_segment_itim_source_start = LOADADDR(.itim) );
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );

.lalign : {
. = ALIGN(8);
PROVIDE( _data_lma = . );
PROVIDE( metal_segment_data_source_start = . );
} >flash AT>flash :flash

.dalign : {
. = ALIGN(8);
PROVIDE( metal_segment_data_target_start = . );
} >ram AT>flash :ram_init

.data : {
.data : ALIGN(8) {
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
Expand All @@ -147,31 +138,30 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
. = ALIGN(8);
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
} >ram AT>flash :ram_init

PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( metal_segment_data_target_end = . );
PROVIDE( metal_segment_data_source_start = LOADADDR(.data) );
PROVIDE( metal_segment_data_target_start = ADDR(.data) );
PROVIDE( metal_segment_data_target_end = ADDR(.data) + SIZEOF(.data) );

. = ALIGN(8);
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
PROVIDE( metal_segment_bss_target_start = . );

.bss : {
.bss : ALIGN(8) {
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
} >ram AT>ram :ram
PROVIDE( _end = . );
PROVIDE( end = . );
PROVIDE( metal_segment_bss_target_end = . );
PROVIDE( metal_segment_bss_target_start = ADDR(.bss) );
PROVIDE( metal_segment_bss_target_end = ADDR(.bss) + SIZEOF(.bss) );

.stack : {
PROVIDE(metal_segment_stack_begin = .);
. = __stack_size;
. += __stack_size;
PROVIDE( _sp = . );
PROVIDE(metal_segment_stack_end = .);
} >ram AT>ram :ram
Expand Down
12 changes: 12 additions & 0 deletions bsp/freedom-e310-arty/metal.h
Original file line number Diff line number Diff line change
Expand Up @@ -294,6 +294,16 @@ static __inline__ int __metal_driver_sifive_plic0_interrupt_lines(struct metal_i
}
}

static __inline__ int __metal_driver_sifive_plic0_context_ids(int hartid)
{
if (hartid == 0) {
return 0;
}
else {
return -1;
}
}



/* --------------------- sifive_clic0 ------------ */
Expand Down Expand Up @@ -554,6 +564,8 @@ static __inline__ unsigned long __metal_driver_sifive_spi0_pinmux_source_selecto
/* --------------------- sifive_test0 ------------ */


/* --------------------- sifive_trace ------------ */

/* --------------------- sifive_uart0 ------------ */
static __inline__ unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
{
Expand Down
64 changes: 27 additions & 37 deletions bsp/freedom-e310-arty/metal.ramrodata.lds
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ SECTIONS

__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x800;
PROVIDE(__metal_boot_hart = 0);
PROVIDE(__metal_chicken_bit = 0);

Expand Down Expand Up @@ -65,13 +65,21 @@ SECTIONS
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
PROVIDE_HIDDEN ( metal_constructors_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.metal.init_array.*)));
KEEP (*(.metal.init_array));
PROVIDE_HIDDEN ( metal_constructors_end = .);
} >flash AT>flash :flash

.fini_array : {
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
PROVIDE_HIDDEN ( metal_destructors_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.metal.fini_array.*)));
KEEP (*(.metal.fini_array));
PROVIDE_HIDDEN ( metal_destructors_end = .);
} >flash AT>flash :flash

.ctors : {
Expand All @@ -80,6 +88,7 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*(.metal.ctors metal.ctors.*));
} >flash AT>flash :flash

.dtors : {
Expand All @@ -88,39 +97,21 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
KEEP (*(.metal.dtors metal.dtors.*));
} >flash AT>flash :flash



.litimalign : {
. = ALIGN(8);
PROVIDE( metal_segment_itim_source_start = . );
} >flash AT>flash :flash

.ditimalign : {
. = ALIGN(8);
PROVIDE( metal_segment_itim_target_start = . );
} >itim AT>flash :itim_init

.itim_section : {
.itim : ALIGN(8) {
*(.itim .itim.*)
} >itim AT>flash :itim_init

PROVIDE( metal_segment_itim_target_end = . );

PROVIDE( metal_segment_itim_source_start = LOADADDR(.itim) );
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );

.lalign : {
. = ALIGN(8);
PROVIDE( _data_lma = . );
PROVIDE( metal_segment_data_source_start = . );
} >flash AT>flash :flash

.dalign : {
. = ALIGN(8);
PROVIDE( metal_segment_data_target_start = . );
} >ram AT>flash :ram_init

.data : {
.data : ALIGN(8) {
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
Expand All @@ -133,31 +124,30 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
. = ALIGN(8);
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
} >ram AT>flash :ram_init

PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( metal_segment_data_target_end = . );
PROVIDE( metal_segment_data_source_start = LOADADDR(.data) );
PROVIDE( metal_segment_data_target_start = ADDR(.data) );
PROVIDE( metal_segment_data_target_end = ADDR(.data) + SIZEOF(.data) );

. = ALIGN(8);
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
PROVIDE( metal_segment_bss_target_start = . );

.bss : {
.bss : ALIGN(8) {
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
} >ram AT>ram :ram
PROVIDE( _end = . );
PROVIDE( end = . );
PROVIDE( metal_segment_bss_target_end = . );
PROVIDE( metal_segment_bss_target_start = ADDR(.bss) );
PROVIDE( metal_segment_bss_target_end = ADDR(.bss) + SIZEOF(.bss) );

.stack : {
PROVIDE(metal_segment_stack_begin = .);
. = __stack_size;
. += __stack_size;
PROVIDE( _sp = . );
PROVIDE(metal_segment_stack_end = .);
} >ram AT>ram :ram
Expand Down
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