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Merge pull request #359 from sifive/bump-freedom-devicetree-tools
Pull in latest changes from master and forward-port recent changes from v201908-branch
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The [Freedom E310 Arty](https://github.com/sifive/freedom) is a completely open-source | ||
implementation of RISC-V using the Rocket Chip Generator, designed for use with | ||
the [Digilent Arty FPGA Evaluation Kit](https://www.xilinx.com/products/boards-and-kits/arty.html). | ||
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This target is ideal for getting familiarize with RISC-V ISA instructions set and | ||
freedom-metal libraries. It supports: | ||
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- 1 hart with RV32IMAC core | ||
- 4 hardware breakpoints | ||
- 16 local interrupts signal that can be connected to off core complex devices | ||
- Up to 26 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels | ||
- GPIO with 16 interrupt lines | ||
- SPI memory with 1 interrupt line | ||
- Serial port with 1 interrupt line |
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