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RzIL v810 support #4096
RzIL v810 support #4096
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As for tracetesting, I wasn't able to find any good open source V810 emulator. If there is none, we can skip this test. Maybe can craft more convoluted "emulateme" test instead? UPDATE: There is MAME though: https://github.com/mamedev/mame/tree/master/src/devices/cpu/v810 |
We also lack any ELF and analysis tests for this architecture. Might be a good idea also to check if DWARF works too. |
"gpr Reserved_8 .32 164 0\n" | ||
"gpr Reserved_9 .32 168 0\n" | ||
"gpr Reserved_10 .32 172 0\n" | ||
"gpr Reserved_11 .32 176 0\n" | ||
"gpr Reserved_12 .32 180 0\n" | ||
"gpr Reserved_13 .32 184 0\n" | ||
"gpr Reserved_14 .32 188 0\n" | ||
"gpr Reserved_15 .32 192 0\n" | ||
"gpr Reserved_16 .32 196 0\n" | ||
"gpr Reserved_17 .32 200 0\n" | ||
"gpr Reserved_18 .32 204 0\n" | ||
"gpr Reserved_19 .32 208 0\n" | ||
"gpr Reserved_20 .32 212 0\n" | ||
"gpr Reserved_21 .32 216 0\n" | ||
"gpr Reserved_22 .32 220 0\n" | ||
"gpr Reserved_23 .32 224 0\n" |
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why these?
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Since several instructions need to read and write SR registers with index, these reversed registers need to be at the location.
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the v810 binary: rizinorg/rizin-testbins#138 |
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The RzIL part looks fine. Could you please extend also ELF and DWARF loaders to load debug information for these ELF files?
I wonder if you can also compile that float_ex1.c
with and without DWARF to check the debuginfo information loading and the analysis precision.
Is it going in this PR? |
This v810-gcc 4.9.4 looks buggy and can't generate DWARF.
|
Ok, ignore my suggestion about DWARF and just add ELF detection and analysis test (functions/variables/etc) in a separate PR as we agreed. |
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