sw: Add Snitch runtime

sw/tests/bare-metal/snitchd/Makefile

@@ -0,0 +1,30 @@
+
+RISCV_PREFIX  ?=
+RISCV_CC      ?= clang
+RISCV_OBJDUMP ?= llvm-objdump
+RISCV_OBJCOPY ?= llvm-objcopy
+RISCV_AR      ?= llvm-ar
+RISCV_AS      ?= llvm-as
+
+RISCV_FLAGS    ?= -g -O2 -mcpu=snitch -mabi=ilp32d -march=rv32imafd_zfh1p0_xfrep0p1_xssr0p1_xdma0p1_xfalthalf0p1_xfquarter0p1_xfaltquarter0p1_xfvecsingle0p1_xfvechalf0p1_xfvecalthalf0p1_xfvecquarter0p1_xfvecaltquarter0p1_xfauxhalf0p1_xfauxalthalf0p1_xfauxquarter0p1_xfauxaltquarter0p1_xfauxvecsingle0p1_xfauxvechalf0p1_xfauxvecalthalf0p1_xfauxvecquarter0p1_xfauxvecaltquarter0p1_xfexpauxvechalf0p1_xfexpauxvecalthalf0p1_xfexpauxvecquarter0p1_xfexpauxvecaltquarter0p1 -ffreestanding --sysroot=$(HERO_INSTALL)/rv32imafd-ilp32d/riscv32-unknown-elf
+RISCV_LDFLAGS  ?= -static -nostdlib -L$(HERO_INSTALL)/lib/clang/15.0.0/rv32imafd-ilp32d/lib/ -lclang_rt.builtins-riscv32
+RISCV_CCFLAGS  ?= $(RISCV_FLAGS) -DPRINTF_DISABLE_SUPPORT_EXPONENTIAL -Iruntime
+
+all: bin/libomptarget_device.a
+
+bin:
+	mkdir $@
+
+bin/libomptarget_device.a: runtime/link.ld runtime/crt0.S omptarget.c runtime/printf.c runtime/sw_mailbox.c | bin
+	$(RISCV_CC) -c $(RISCV_CCFLAGS) $(DEFINES_$*) runtime/crt0.S -o bin/crt0.o
+	$(RISCV_CC) -c $(RISCV_CCFLAGS) $(DEFINES_$*) runtime/printf.c -o bin/printf.o
+	$(RISCV_CC) -c $(RISCV_CCFLAGS) $(DEFINES_$*) runtime/sw_mailbox.c -o bin/sw_mailbox.o
+	$(RISCV_CC) -c $(RISCV_CCFLAGS) $(DEFINES_$*) omptarget.c -o bin/omptarget.o
+	llvm-ar rcs $@ bin/crt0.o bin/printf.o bin/sw_mailbox.o bin/omptarget.o
+	$(RISCV_OBJDUMP) -S -D $@ > bin/libomptarget_device.dump
+
+clean:
+	rm bin/*
+.PHONY: clean
+
+.PRECIOUS: bin/*

sw/tests/bare-metal/snitchd/omptarget.c

@@ -0,0 +1,97 @@
+#include <inttypes.h>
+#include "runtime.h"
+#include "sw_mailbox.h"
+#include "printf.h"
+
+void _putchar(char byte) {
+    snrt_putchar((uint32_t)byte);
+}
+
+extern volatile uint8_t l1_alloc_base;
+const uint32_t __attribute__((section(".init_l1"))) *l1_alloc_base_ptr = (uint32_t *) &l1_alloc_base;
+extern volatile uint32_t jump_address;
+const uint32_t __attribute__((section(".init_l1"))) *jump_address_ptr  = (uint32_t *) &jump_address;
+extern volatile uint32_t scratch_reg;
+const uint32_t __attribute__((section(".init_l1"))) *scratch_reg_ptr   = (uint32_t *) &scratch_reg;
+
+
+volatile uint32_t lock __attribute__ ((section(".noinit_l1")));
+static volatile uint32_t quit __attribute__ ((section(".noinit_l1")));
+
+volatile void (*offloadFn)(uint64_t) __attribute__ ((section(".noinit_l1")));
+volatile uint64_t offloadArgs __attribute__ ((section(".noinit_l1")));
+
+static int gomp_offload_manager(uint32_t core_idx) {
+
+  uint32_t cmd = (uint32_t)NULL;
+  uint32_t data;
+  unsigned nbOffloadRabMissHandlers = 0x0;
+  uint32_t offload_rab_miss_sync = 0x0U;
+  int cycles = 0, dma_wait_cycles = 0;
+  uint32_t issue_fpu, dma_busy;
+
+  while (1) {
+    if(core_idx == 8) {
+        mailbox_read((unsigned int *)&cmd, 1);
+        // printf("\n\rReceived command: %x\n\r", cmd);
+        cycles = read_csr(mcycle);
+        if (MBOX_DEVICE_STOP == cmd) {
+            quit = 1;
+            // Wake up the other cores (pre offload barrier)
+            pulp_barrier();
+            break;
+        } else if (MBOX_DEVICE_LOGLVL == cmd) {
+        mailbox_read((unsigned int *)&data, 1);
+        continue;
+        } else if (MBOX_DEVICE_START != cmd) {
+        break;
+        }
+        mailbox_read((unsigned int *)&offloadFn, 1);
+        mailbox_read((unsigned int *)&offloadArgs, 1);
+        mailbox_read((unsigned int *)&nbOffloadRabMissHandlers, 1);
+
+        if (offloadArgs != 0x0) {
+        }
+        cycles = read_csr(mcycle);
+        dma_wait_cycles = 0;
+
+    }
+
+    pulp_barrier();
+
+    if(quit)
+        break;
+
+    offloadFn(offloadArgs);
+
+    pulp_barrier();
+
+    if(core_idx == 8) {
+        mailbox_write(MBOX_DEVICE_DONE);
+        cycles = read_csr(mcycle) - cycles;
+        mailbox_write(cycles);
+        mailbox_write(dma_wait_cycles);
+    }
+  }
+    //exit here
+    // CORRECT
+  return 0;
+}
+
+int main() {
+    uint32_t core_idx = pulp_get_core_id();
+    int err = 0;
+
+    if(core_idx == 8) {
+        lock = 0;
+        quit = 0;
+        struct l3_layout *l3l_ptr = (struct l3_layout *)(*scratch_reg_ptr);
+        g_a2h_rb =   (struct ring_buf*)l3l_ptr->a2h_rb;
+        g_a2h_mbox = (struct ring_buf*)l3l_ptr->a2h_mbox;
+        g_h2a_mbox = (struct ring_buf*)l3l_ptr->h2a_mbox;
+    }
+
+    gomp_offload_manager(core_idx);
+
+    return 0;
+}

sw/tests/bare-metal/snitchd/runtime/crt0.S

@@ -0,0 +1,165 @@
+# Copyright 2020 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+.section .text.init
+_start:
+    .globl _start
+
+    la      t0, crt0.trap
+    csrw    mtvec, t0
+
+    fence
+    fence.i
+
+    # Initialize global pointer
+crt0.init_global_pointer:
+    .option push
+    .option norelax
+1:  auipc     gp, %pcrel_hi(__global_pointer$)
+    addi      gp, gp, %pcrel_lo(1b)
+    .option pop
+
+    # Initialize integer registers
+crt0.init_int_regs:
+    li        x1, 0
+    li        x4, 0
+    li        x5, 0
+    li        x6, 0
+    li        x7, 0
+    li        x8, 0
+    li        x9, 0
+    li        x10, 0
+    li        x11, 0
+    li        x12, 0
+    li        x13, 0
+    li        x14, 0
+    li        x15, 0
+    li        x16, 0
+    li        x17, 0
+    li        x18, 0
+    li        x19, 0
+    li        x20, 0
+    li        x10, 0
+    li        x21, 0
+    li        x22, 0
+    li        x23, 0
+    li        x24, 0
+    li        x25, 0
+    li        x26, 0
+    li        x27, 0
+    li        x28, 0
+    li        x29, 0
+    li        x30, 0
+    li        x31, 0
+
+    # Initialize float registers (if the core has F/D extension)
+crt0.init_float_regs:
+    csrr      t0, misa
+    andi      t0, t0, (1 << 5)  # F/D flag is bit 5
+    beqz      t0, 1f
+    fmv.s.x   f0, x0
+    fmv.s.x   f1, x0
+    fmv.s.x   f2, x0
+    fmv.s.x   f3, x0
+    fmv.s.x   f4, x0
+    fmv.s.x   f5, x0
+    fmv.s.x   f6, x0
+    fmv.s.x   f7, x0
+    fmv.s.x   f8, x0
+    fmv.s.x   f9, x0
+    fmv.s.x   f10, x0
+    fmv.s.x   f11, x0
+    fmv.s.x   f12, x0
+    fmv.s.x   f13, x0
+    fmv.s.x   f14, x0
+    fmv.s.x   f15, x0
+    fmv.s.x   f16, x0
+    fmv.s.x   f17, x0
+    fmv.s.x   f18, x0
+    fmv.s.x   f19, x0
+    fmv.s.x   f20, x0
+    fmv.s.x   f10, x0
+    fmv.s.x   f21, x0
+    fmv.s.x   f22, x0
+    fmv.s.x   f23, x0
+    fmv.s.x   f24, x0
+    fmv.s.x   f25, x0
+    fmv.s.x   f26, x0
+    fmv.s.x   f27, x0
+    fmv.s.x   f28, x0
+    fmv.s.x   f29, x0
+    fmv.s.x   f30, x0
+    fmv.s.x   f31, x0
+1:
+
+    # Read hartid and number of cores in the cluster.
+crt0.init_core_info:
+    li        t0, 0x10  # load cluster's hartid offset
+    csrr      a0, mhartid  # shift core's hartid such that first core is 0
+    sub       a0, a0, t0
+    li        a1, 9  # load the number of cores per cluster
+
+crt0.big_hack:
+    li        t3, 0x51020000
+    la        t4, tcdm_end_address_reg
+    sw        t3, 0(t4)
+    li        t3, 0x51020190
+    la        t4, barrier_reg
+    sw        t3, 0(t4)
+
+    # Read hartid and number of cores in the cluster.
+crt0.init_stack:
+    la        sp, tcdm_end_address_reg  # load stack top from peripheral register
+    lw        sp, 0(sp)
+    addi      sp, sp, -8  # set 8 bytes aside for the main return value
+    sw        zero, 0(sp)
+    slli      t0, a0, 10  # set 2**10 bytes of stack space aside for each hart
+    sub       sp, sp, t0
+    slli      t0, a0, 3   # misalign stacks in the TCDM to reduce banking conflicts
+    add       sp, sp, t0
+
+    # Synchronize cores.
+crt0.pre_barrier:
+    csrr x0, 0x7C2
+    la        t0, barrier_reg
+    lw        t0, 0(t0)
+    mv        zero, t0
+
+    # Execute the main function.
+crt0.main:
+    call      main
+    la        s0, tcdm_end_address_reg  # add return value to special slot
+    lw        s0, 0(s0)
+    addi      s0, s0, -8
+    #amoadd.w  zero, a0, (s0)
+    #la        t0, fetch_enable_reg
+    #sw        zero, 0(t0)
+
+    # Synchronize cores.
+crt0.post_barrier:
+    csrr x0, 0x7C2
+    la        t0, barrier_reg
+    lw        t0, 0(t0)
+    mv        zero, t0
+
+    # Write execution result to EOC register.
+#crt0.end:
+#    la        t0, cluster_base_hart_id_reg
+#    lw        t0, 0(t0)
+#    csrr      t1, mhartid
+#    bne       t0, t1, crt0.loop_back  # only first core writes to EOC address
+#    #lw        a0, 0(s0)  # load accumulated return value from special slot
+#    slli      a0, a0, 0  # shift in a 1 LSB to indicate execution completion
+#    ori       a0, a0, 1
+#    la        t0, eoc_address
+#    sw        a0, 0(t0)
+#    mv        t0, zero
+#
+#crt0.loop_back:
+#    la        t0, bootrom_start 
+#    jr        t0
+#
+
+crt0.trap:
+    j crt0.trap