Efabless

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217 repositories

EF_UART
Public
Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP
Verilog
•
Apache License 2.0
•3•5•9•1•Updated Jan 11, 2025Jan 11, 2025
IHP-Open-PDK
Public
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
HTML
•
Apache License 2.0
•67•0•1•0•Updated Jan 10, 2025Jan 10, 2025
openlane-metrics
Public
Repository to store metric results for OpenLane 2.0.0+
0•0•0•0•Updated Jan 9, 2025Jan 9, 2025
openlane2
Public
The next generation of OpenLane, rewritten from scratch with a modular architecture
flow asic eda verilog vlsi pnr silicon lvs flows sta
Python
•
Apache License 2.0
•43•253•81•11•Updated Jan 9, 2025Jan 9, 2025
openlane2-step-unit-tests
Public
Step-specific Unit Tests for OpenLane 2.0.0+
Verilog
•
Apache License 2.0
•0•0•0•1•Updated Jan 9, 2025Jan 9, 2025
BusWrap
Public
Python
•0•5•5•0•Updated Jan 9, 2025Jan 9, 2025
EF_IP_UTIL
Public
A set of utilities that can be used to develop digital IPs in Verilog HDL.
Verilog
•0•0•0•0•Updated Jan 9, 2025Jan 9, 2025
ipm
Public
Open-source IPs Package Manager (IPM)
Python
•
Apache License 2.0
•2•14•6•3•Updated Jan 9, 2025Jan 9, 2025
volare
Public
Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
version-manager pdk openlane pdks python
Python
•
Apache License 2.0
•7•63•5•4•Updated Jan 9, 2025Jan 9, 2025
EF_UVM
Public
Python
•1•2•0•0•Updated Jan 9, 2025Jan 9, 2025
EF_SPI
Public
Verilog
•0•0•5•0•Updated Jan 8, 2025Jan 8, 2025
central_CI
Public
0•0•1•5•Updated Jan 8, 2025Jan 8, 2025
EF_TMR32
Public
Verilog
•
Apache License 2.0
•1•0•3•0•Updated Jan 8, 2025Jan 8, 2025
sky130_klayout_pdk
Public
Skywaters 130nm Klayout PDK
pdk skywaters chipdesign
Python
•
Apache License 2.0
•13•20•6•1•Updated Jan 8, 2025Jan 8, 2025
EF_GPIO8
Public
A generic 8-bit General Purpose I/O (GPIO) Peripheral
Verilog
•
Apache License 2.0
•1•1•1•0•Updated Jan 8, 2025Jan 8, 2025
skywater-pdk-libs-sky130_fd_io
Public
Verilog
•
Apache License 2.0
•8•1•0•0•Updated Jan 8, 2025Jan 8, 2025
chipcraft---mest-course
Public
TL-Verilog
•
Creative Commons Zero v1.0 Universal
•9•31•0•0•Updated Jan 6, 2025Jan 6, 2025
caravel-sim-infrastructure
Public
HTML
•
Apache License 2.0
•4•1•1•0•Updated Jan 6, 2025Jan 6, 2025
openlane2-ci-designs
Public
Continuous Integration Designs for OpenLane 2.0.0 or higher
Verilog
•1•0•0•1•Updated Jan 5, 2025Jan 5, 2025
MS_WDT32
Public
A simple WatchDog Timer (WDT)
Verilog
•
Apache License 2.0
•1•0•0•0•Updated Jan 2, 2025Jan 2, 2025
skywater-pdk-libs-sky130_fd_pr
Public
Python
•
Apache License 2.0
•23•7•7•0•Updated Jan 1, 2025Jan 1, 2025
caravel_SI_testing
Public
C
•1•2•3•4•Updated Dec 30, 2024Dec 30, 2024
nix-eda
Public
Nix derivations for EDA tools
nix eda electronic-design-automation nix-flake
Nix
•
Apache License 2.0
•3•8•2•0•Updated Dec 24, 2024Dec 24, 2024
caravel_user_project
Public template
https://caravel-user-project.readthedocs.io
Verilog
•
Apache License 2.0
•332•186•84•22•Updated Dec 22, 2024Dec 22, 2024
caravel_mgmt_soc_litex
Public
https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
Verilog
•
Apache License 2.0
•15•26•23•10•Updated Dec 18, 2024Dec 18, 2024
openframe_timer_example
Public
Example digital project for the Efabless Caravel "openframe" harness
Verilog
•
Apache License 2.0
•12•4•3•0•Updated Dec 11, 2024Dec 11, 2024
caravel_user_project_analog
Public template
Verilog
•
Apache License 2.0
•89•45•6•2•Updated Dec 11, 2024Dec 11, 2024
skywater-pdk-libs-sky130_fd_sc_hd
Public
Verilog
•
Apache License 2.0
•30•2•1•0•Updated Dec 11, 2024Dec 11, 2024
caravel
Public
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
magic yosys caravel picorv32 openroad vexriscv openram sky130
Verilog
•
Apache License 2.0
•69•301•93•14•Updated Dec 10, 2024Dec 10, 2024
cace
Public
Circuit Automatic Characterization Engine
Python
•
Apache License 2.0
•6•46•23•1•Updated Dec 6, 2024Dec 6, 2024