stm32f1: Enable non-halting SRAM access for RTT on tested chips

* Tested chips include GD32F103CB, GD32F303CC, GD32E508ZE

src/target/stm32f1.c

@@ -286,8 +286,10 @@ bool gd32f1_probe(target_s *target)
 	switch (device_id) {
 	case 0x414U: /* GD32F30x_HD, High density */
 	case 0x430U: /* GD32F30x_XD, XL-density */
-		target->driver = "GD32F3";
+		target->driver = "GD32F3 HD/XD";
 		block_size = 0x800;
+		/* On this SoC, Cortex-M4F allows SRAM access without halting */
+		target->target_options |= TOPT_NON_HALTING_MEM_IO;
 		break;
 	case 0x418U: /* Connectivity Line */
 		target->driver = "GD32F2";
@@ -297,14 +299,19 @@ bool gd32f1_probe(target_s *target)
 		if ((target->cpuid & CORTEX_CPUID_PARTNO_MASK) == CORTEX_M23)
 			target->driver = "GD32E230"; /* GD32E230, 64 KiB max in 1 KiB pages */
 		else if ((target->cpuid & CORTEX_CPUID_PARTNO_MASK) == CORTEX_M4) {
-			target->driver = "GD32F3";
+			target->driver = "GD32F3 MD";
 			block_size = 0x800;
-		} else
+		} else {
 			target->driver = "GD32F1"; /* GD32F103, 1 KiB pages */
+			/* On this SoC, Cortex-M3 allows SRAM access without halting */
+			target->target_options |= TOPT_NON_HALTING_MEM_IO;
+		}
 		break;
 	case 0x444U: /* GD32E50x_CL, 512 KiB max in 8 KiB pages */
 		target->driver = "GD32E5";
 		block_size = 0x2000;
+		/* On this SoC, Cortex-M33 allows SRAM access without halting */
+		target->target_options |= TOPT_NON_HALTING_MEM_IO;
 		break;
 	default:
 		return false;