diff --git a/core/commit_stage.sv b/core/commit_stage.sv
index d10ac6a44a..8592ed43cb 100644
--- a/core/commit_stage.sv
+++ b/core/commit_stage.sv
@@ -338,8 +338,8 @@ module commit_stage
     exception_o.tval  = '0;
     exception_o.tval2 = '0;
     exception_o.tinst = '0;
-    exception_o.gva   = 1'b0;
-    exception_o.priv_lvl  = riscv::PRIV_LVL_M;
+    exception_o.gva = 1'b0;
+    exception_o.priv_lvl = riscv::PRIV_LVL_M;
     exception_o.trap_to_v = 1'b0;
 
     // we need a valid instruction in the commit stage