Add support for alternative bus interfaces

[jbush001]

Currently the cache uses the AMBA AXI bus protocol to interface with memory. As a proof of concept, it would be nice to also support other bus interfaces like the open Wishbone protocol. Ideally the bus could be selected with a build flag.

Currently all of the bus functionality is consolidated in one module: l2_axi_bus_interface.sv, which is a deliberate decision to simplify using other bus interfaces. I considered breaking this into two parts: one that handles the queues and interfacing with the rest of the L2 pipeline, and the other that handles bus handshaking. But this would seem to preclude some optimizations that allow multiple transactions to be outstanding (#74). The alternative would be to create a separate bus_interface module for each other bus technology. Configuring this in the design is a big clunky though (especially exposing it conditionally via the port interface, which will not work well with Verilog mode AUTO expansion).

Issue #133 relates to using a standard bus for I/O transactions, which would also need to transition to Wishbone.