sec-conclusion.tex

\section{Conclusion and Future Work}
In this paper, we have improved the existing automatic pipelining tool in Chisel by adding functionality that allows the tool to automatically find a close-to-optimal placement of the pipeline registers with minimal manual specification. The improved Chisel automatic pipelining tool allows the designer to have to only label a small subset of the Chisel graph nodes in his design and automatically obtain a pipelined design that has close-to-optimal pipeline register placement based on real delay data gathered from Chisel backannotation. This presents a step towards further decreasing design effort for pipelining designs over the exisiting automatic pipelining tool.

The results of the Chisel backannotator show that it can accurately calculate the critical path delays of most of designs in the Chisel tutorial except some designs such as Adder, BasicALU, and Risc. However, it does not mean each Chisel graph node has the exact delay numbers due to the arrival time estimation for missing signals, which may make the automatic pipelining tool yield non-optimal results. In addition, the delay numbers obtained from the backannotator are not realistic because the design is synthesized with simple design environment and constraints.  

To obtain realistic delay numbers, we will backannotate Chisel graphs with the delay information after placement and routing, which affects circuit timing significantly. To improve the Chisel backannotator's accuracy, we will develop more elaborated delay estimation for missing signals by mapping them to appropriate nets in the gate netlists. The observation is there are more nets than missing signals between two non-missing signals. We will use statical methods to map missing signals into their substitution nets. Also, the Chisel backannotator will have a mapping from logic cells to Chisel nodes, which is used to calculate not only delays, but area and power numbers.

Independent evaluation of the automatic pipeline register placement tool shows that the tool is capable of achieving reasonably optimal pipeline register placement for both simple finite state machines and more complex processor designs, when constraints on the tool are taken into consideration. When the tool is used with real delay data obtained with Chisel backannotation, the tool still achieves close-to-optimal pipeline register placement on designs that do not have their critical path dominated by paths that the tool cannot reach.

In future work, we plan to improve the automatic pipeline register placement by removing the restrictions on the tool preventing it from moving I/O nodes and architectural register read and write points. This will decrease the constraints on where the tool can place the pipeline registers and allow the tool to achieve more optimal pipeline register placements on complex designs. We also want to do a study of how the tool performs when it is combined with VLSI retiming tools.