riscv64_inorder_soc.cfg

/* VM configuration file */
{
	version: 1,
	machine: "riscv64", /* riscv32, riscv64 */
	memory_size: 2048, /* MB */
	bios: "riscv64-unknown-linux-gnu/bbl64.bin",
	kernel: "riscv64-unknown-linux-gnu/kernel-riscv64.bin",
	cmdline: "console=hvc0 root=/dev/vda rw",
	drive0: { file: "riscv64-unknown-linux-gnu/riscv64.img" },
	eth0: { driver: "user" },

	core: {
		name: "64-bit inorder riscv CPU",
		type: "incore", /* incore, oocore */
		cpu_freq_mhz: 1000,
		rtc_freq_mhz: 10,

		incore : {
			num_cpu_stages: 5, /* 5, 6 */
		},

		oocore: {
			iq_size: 16,
			iq_issue_ports: 3,
			rob_size: 64,
			rob_commit_ports:4,
			lsq_size: 16,
		},

		/* Note: Latencies for functional units, caches and memory are specified in CPU cycles */
		functional_units: {
			num_alu_stages: 1,
			alu_stage_latency: "1",
	
			num_mul_stages: 1,
			mul_stage_latency: "4",
	
			num_div_stages: 1,
			div_stage_latency: "67",
	
			/* Note: This will create a pipelined FP-FMA unit with 4 stages with a
			 * latency of 1 CPU cycle(s) per stage */
			num_fpu_fma_stages: 4,
			fpu_fma_stage_latency: "1,1,1,1",
	
			/* Note: FP-ALU is non-pipelined */
			fpu_alu_stage_latency: {
				fadd: 2,
				fsub: 2,
				fmul: 2,
				fdiv: 8,
				fsqrt: 8,
				fsgnj: 2,
				fmin: 4,
				fmax: 4,
				feq: 2,
				flt: 2,
				fle: 2,
				cvt: 2,
				fcvt: 2,
				fmv: 2,
				fclass: 1,
			},

			/* Latency for RISC-V SYSTEM opcode instructions (includes CSR and privileged instructions)*/
			system_insn_latency: 3,
		},
	
		bpu: {
			enable: "true", /* true, false */
			flush_on_context_switch: "false", /* true, false */

			btb: {
				size: 32,
				ways: 2,
				eviction_policy: "lru", /* lru, random */
			},
	
			bpu_type: "bimodal", /* bimodal, adaptive */
	
			bimodal: {
				bht_size: 256,
			},
	
			adaptive: {
				ght_size: 1,
				pht_size: 1,
				history_bits: 2,
				aliasing_func_type: "xor", /* xor, and, none */

			    /* Given config for adaptive predictor will create a Gshare predictor:
				*	1) global history table consisting of one entry, entry includes a 2-bit history register
				*	2) pattern history table consisting of one entry, entry includes an array of 4 saturating counters
				* 	3) value of history register will be `xor` ed with branch PC to index into the array of saturating counters
				*/
			},
	
			ras_size: 6, /* value 0 disables RAS */
		},
	
		caches: {
			enable_l1_caches: "true", /* true, false */
			allocate_on_write_miss: "true", /* true, false */
			write_policy: "writeback", /* writeback, writethrough */
			line_size: 64, /* Bytes */
	
			icache: {
				size: 32, /* KB */
				ways: 4,
				latency: 1,
				eviction: "lru", /* lru, random */
			},
	
			dcache: {
				size: 32, /* KB */
				ways: 8,
				latency: 1,
				eviction: "lru", /* lru, random */
			},
	
			l2_shared_cache: {
				enable: "true",
				size: 256, /* KB */
				ways: 16,
				latency: 5,
				eviction: "lru", /* lru, random */
			},
		},
	},

	memory: {
		tlb_size: 32,

		/* Memory controller burst-length in bytes */ 
		/* Note: This is automatically set to cache line size if caches are enabled */
		burst_length: 64, /* Bytes */

		base_dram_model: {
			mem_access_latency: 50,
		},

		dramsim3: {
			config_file: "DRAMsim3/configs/DDR4_4Gb_x16_2400.ini",
		},

		ramulator: {
			config_file: "ramulator/configs/DDR4-config.cfg",
		},
	},
}